Dynamic Power Reduction with Sequential Clock Gating Synthesis Using Time Expansion

Abstract

Power reduction is very important in recent VLSI design, and dynamic power takes a large part of total power. Clock gating is usually applied to reduce dynamic power by blocking unnecessary clock change. If the change of a clock can be stopped, then the power of clock line and connected registers can be saved. This research focuses on a method for stability-based sequential clock gating synthesis method is proposed. It uses time expansion to detect disable signals (clock gating signals) of past time step. Compared to most of current research about combinational clock gating, it finds stability-based sequential clock gating condition. The proposed method and the original Hurst’s method are implemented in Matlab programs and applied to 7 ISCAS89 benchmark circuits. Experimental results show that the proposed method can have from 5.80% to 48.77% power reduction with area overhead from 1.33% to 6.46% compared with original circuits; from 2.86% to 38.14% power reduction with area overhead from 0.94% to 4.78% compared with Hurst’s method.